1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a shifting circuit.
2. Description of the Related Art
A voltage level, which is externally supplied to a semiconductor device, is getting lower as power consumption of the semiconductor device becomes lower. Therefore, the semiconductor device includes a level shifting circuit capable of converting the externally supplied voltage having a preset level into an internal voltage having an appropriate level for internal circuits of the semiconductor device. For example, the level shifting circuit converts a signal having low voltage level into a signal having higher voltage level using a boosted voltage. Such a level shifting circuit serves as an interface for circuits using various voltage levels.
FIG. 1 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, the conventional semiconductor device includes first to fifth level shifting circuits 10A to 10E corresponding to a first region (not shown) and sixth to tenth level shifting circuits 20A to 20E corresponding to a second region (not shown).
The first to fifth level shifting circuits 10A to 10E shifts levels of first to fifth internal control signals SAE1, SAE, SADRVPCGB, MATSEL and IOSWEN to one of first and second boosted voltage VPP and VPPY and generates first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L in response to a first region identification signal LAXF<0>.
For example, the first level shifting circuit 10A includes a first input section 10A_1, a first level shifter 10_3 and a first output section 10A_5. The first input section 10A_1 selectively receives a pull-up enable signal SAE1 in response to the first region identification signal LAXF<0>. The first level shifter 10A_3 shifts level of the output signal of the first input section 10A_1 to the first boosted voltage VPP. The first output section 10A_5 outputs the output signal of the first level shifter 10A_3 as the first pull-up driving signal SAP_L.
The second level shifting circuit 10B includes a second input section 10B_1, a second level shifter 10B_3 and a second output section 10B_5. The second input section 10B_1 selectively receives a pull-down enable signal SAE in response to the first region identification signal LAXF<0>. The second level shifter 10B_3 shifts level of the output signal of the second input section 10B_1 to the second boosted voltage VPPY. The second output section 10B_5 outputs the output signal of the second level shifter 10B_3 as the first pull-down driving signal SAN_L.
The third level shifting circuit 10C includes a third input section 10C_1, a third level shifter 10C_3 and a third output section 10C_5. The third input section 10C_1 selectively receives a control signal SADRVPCGB for sensing and amplifying in response to the first region identification signal LAXF<0>. The third level shifter 10C_3 shifts level of the output signal of the third input section 10C_1 to the second boosted voltage VPPY. The third output section 10C_5 outputs the output signal of the third level shifter 10C_3 as the first precharge signal SADRVPCG_L for sensing and amplifying.
The fourth level shifting circuit 10D includes a fourth input section 10D_1, a fourth level shifter 10D_3 and a fourth output section 10D_5. The fourth input section 10D_1 selectively receives a mat selection signal MATSEL in response to the first region identification signal LAXF<0>. The fourth level shifter 10D_3 shifts level of the output signal of the fourth input section 10D_1 to the second boosted voltage VPPY. The fourth output section 10D_5 outputs the output signal of the fourth level shifter 10D_3 as the first precharge signal BLEQ_L.
The fifth level shifting circuit 10E includes a fifth input section 10E_1, a fifth level shifter 10E_3 and a fifth output section 10E_5. The fifth input section 10E_1 selectively receives an enable signal IOSWEN for switching in response to the first region identification signal LAXF<0>. The fifth level shifter 10E_3 shifts level of the output signal of the fifth input section 10E_1 to the second boosted voltage VPPY. The fifth output section 10E_5 outputs the output signal of the fifth level shifter 10E_3 as the first switching signal IOSW_L.
The sixth to tenth level shifting circuits 20A to 20E shifts levels of the first to fifth internal control signals SAE1, SAE, SADRVPCGB, MATSEL and IOSWEN to one of the first and second boosted voltage VPP and VPPY and generates sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R in response to a second region identification signal LAXF<1>.
For example, the sixth level shifting circuit 20A includes a sixth input section 20A_1, a sixth level shifter 20A_3 and a sixth output section 20A_5. The sixth input section 20A_1 selectively receives the pull-up enable signal SAE1 in response to the second region identification signal LAXF<1>. The sixth level shifter 20A_3 shifts level of the output signal of the sixth input section 20A_1 to the first boosted voltage VPP. The sixth output section 20A_5 outputs the output signal of the sixth level shifter 20A_3 as the second pull-up driving signal SAP_R.
The seventh level shifting circuit 20B includes a seventh input section 20B_1, a seventh level shifter 20B_3 and a seventh output section 20B_5. The seventh input section 20B_1 selectively receives the pull-down enable signal SAE in response to the second region identification signal LAXF<1>. The seventh level shifter 20B_3 shifts level of the output signal of the seventh input section 20B_1 to the second boosted voltage VPPY. The seventh output section 20B_5 outputs the output signal of the seventh level shifter 20B_3 as the second pull-down driving signal SAN_R.
The eighth level shifting circuit 20C includes an eighth input section 20C_1, an eighth level shifter 20C_3 and an eighth output section 20C_5. The eighth input section 20C_1 selectively receives the control signal SADRVPCGB for sensing and amplifying in response to the second region identification signal LAXF<1>. The eighth level shifter 20C_3 shifts level of the output signal of the eighth input section 20C_1 to the second boosted voltage VPPY. The eighth output section 20C_5 outputs the output signal of the eighth level shifter 20C_3 as the second precharge signal SADRVPCG_R for sensing and amplifying.
The ninth level shifting circuit 20D includes a ninth input section 20D_1, a ninth level shifter 20D_3 and a ninth output section 20D_5. The ninth input section 20D_1 selectively receives the mat selection signal MATSEL in response to the second region identification signal LAXF<1>. The ninth level shifter 20D_3 shifts level of the output signal of the ninth input section 20D_1 to the second boosted voltage VPPY. The ninth output section 20D_5 outputs the output signal of the ninth level shifter 20D_3 as the second precharge signal BLEQ_R.
The tenth level shifting circuit 20E includes a tenth input section 20E_1, a tenth level shifter 20E_3 and a tenth output section 20E_5. The tenth input section 20E_1 selectively receives the enable signal IOSWEN for switching in response to the second region identification signal LAXF<1>. The tenth level shifter 20E_3 shifts level of the output signal of the tenth input section 20E_1 to the second boosted voltage VPPY. The tenth output section 20E_5 outputs the output signal of the tenth level shifter 20E_3 as the second switching signal IOSW_R.
Operation of the conventional semiconductor device is described as follows.
When the first region identification signal LAXF<0> is enabled, the first to fifth level shifting circuits 10A to 10E shifts levels of first to fifth internal control signals SAE1, SAE, SADRVPCGB, MATSEL and IOSWEN to one of first and second boosted voltage VPP and VPPY and outputs the level-shifted signal's as the first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L.
A first internal circuit (not shown) located in the first region performs a preset operation in response to the first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L. For example, the first internal circuit performs a write operation to write into a memory cell, data externally input or performs a read operation to read out data written in the memory cell to the external in response to the first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L.
When the second region identification signal LAXF<1> is enabled, the sixth to tenth level shifting circuits 20A to 20E shifts levels of the first to fifth internal control signals SAE1, SAE, SADRVPCGB, MATSEL and IOSWEN to one of the first and second boosted voltage VPP and VPPY and outputs the level-shifted signals as the sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R.
A second internal circuit (not shown) located in the second region performs a preset operation in response to the sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R, IOSW_R. For example, the second internal circuit performs a write operation to write into a memory cell data externally input or performs a read operation to read out data written in the memory cell to the external in response to the sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R.
There is a problem in such conventional semiconductor device as follows.
The conventional semiconductor device includes the first to tenth level shifting circuits 10A to 10E and 20A to 20E to generate the first to tenth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L, IOSW_L, SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R, which means that the conventional semiconductor device includes one level shifting circuit per one internal assignment signal. This is due to the first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L being assigned to the first region while the sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R are assigned to the second region even though the first to fifth internal assignment signals SAP_L, SAN_L, SADRVPCG_L, BLEQ_L and IOSW_L and the sixth to tenth internal assignment signals SAP_R, SAN_R, SADRVPCG_R, BLEQ_R and IOSW_R are respectively similar to each other.
Such a conventional semiconductor device needs a great amount of space for a plurality level shifting circuits 10A to 10E and 20A to 20E to be disposed therein according to regions.